1. Technical Field
This invention relates to the field of multi-processor systems, and in particular to systems and methods for selecting a bootstrap processor in multi-processor systems.
2. Background Art
Advanced computer systems increasingly rely on multiple processors to provide the computational power necessary to meet the demands of the applications they run. In these systems, processing functions are distributed among the component processors to minimize bottle-necks at any one processor. One approach to multi-processing that has been especially successful treats each processor in the system as equivalent. These systems are referred to as symmetric multi-processor (SMP) systems since the different processors are indistinguishable for purposes of scheduling and executing code. This equivalency greatly facilitates the balancing of work loads among the processors and simplifies the requirements of the operating system. Since all processors are treated as equivalents for executing threads, additional processors may be added to SMP systems without altering the software. This ability to increase the system's processing power easily by adding resources, e.g. processors, is referred to as scalability.
An element of asymmetry in SMP systems is introduced by the need to select a single processor to bootstrap the system. At system start-up and whenever the system is reset, each processor in an SMP system typically is responsible for determining that its internal components and interfaces are functioning properly. The bootstrap processor (BSP) is unique in that it handles initialization procedures for the system as a whole. These procedures include checking the integrity of memory, identifying properties of the system logic, loading the operating system into memory, and starting the remaining processors. Since these functions temporarily introduce asymmetry into SMP systems by assigning a unique role to the BSP, it is desirable to make the selection of the BSP as symmetric as possible.
Conventional systems employ a variety of techniques for selecting a BSP from among the processors of an SMP system. In one SMP system, the processors are coupled through a dedicated, open collector interrupt bus. On reset, each processor asserts an inverted form of an assigned processor identification number (processor ID) onto a shared line of the interrupt bus. As soon as a processor asserting a one on the line detects that another processor is asserting a zero, the first processor relinquishes the line. The processor that survives this arbitration procedure is the processor having the highest valued processor ID. This processor gains control of the bus and sends a message to all processors on the interrupt bus, identifying itself as the BSP. This approach is exemplified by SMP systems based on the Pentium.RTM. Pro microprocessor of Intel corporation.
There are a number of short-comings in this approach to BSP selection. It requires a dedicated interrupt bus. This bus is relatively slow by the standards of today's processor speeds, making the boot process unnecessarily slow. In addition, each bus can only support clusters of up to four processors. Additional processors must be accommodated in separate clusters, and the need for a dedicated interrupt bus makes it difficult to extend the method across multiple clusters.
Another method for selecting the BSP simply designates the processor in a specified slot as the BSP. This strategy introduces a permanent asymmetry into the SMP system, and if the processor in the designated slot fails, no mechanism is provided for designating a different processor as the BSP.
Other methods for selecting BSPs in SMP systems identify the first processor to write to a shared variable as the BSP. In one of these SMP systems, a semaphore is stored at a specified address in memory, and the first of the system's processors to successfully read & set the semaphore value is designated as the BSP. This method, however, requires the use of memory before memory has been tested for reliability by the BSP.
An alternative semaphore-based method has the processors of the SMP system write to a non-volatile memory location, which is usually a register on the system logic or chip set. In this alternative, the chipset includes a read/write register for each processor in the SMP system and a shared register that is accessible to all processors. The processor registers and shared register act together as a semaphore for a critical section of code that must be executed by the BSP. Various algorithms are employed to ensure that only one processor executes the critical code and that this processor's ID is saved in the shared register to identify the BSP.
This method requires that the number of processors in the system be known ahead of time, since a register must be provided in the chipset for each. This limits the scalability of the SMP system and requires additional logic in the chipset for storing the processor ID of the first processor that writes to its assigned register into the shared memory location. It also requires coordination between the chipset logic and the processors prior to boot.
Thus, there is a need for a system and method for selecting a bootstrap processor in a multi-processor system that is scaleable and that can be implemented quickly by the processors of the system, without coordination with memory, the chipset logic, and other implementation dependent components of the multi-processor system.